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INTEGRATED CIRCUITS
DATA SHEET
74LVC2G00 Dual 2-input NAND gate
Product specification Supersedes data of 2003 Nov 17 2004 Sep 23
Philips Semiconductors
Product specification
Dual 2-input NAND gate
FEATURES * Wide supply voltage range from 1.65 V to 5.5 V * 5 V tolerant outputs for interfacing with 5 V logic * High noise immunity * Complies with JEDEC standard: - JESD8-7 (1.65 V to 1.95 V) - JESD8-5 (2.3 V to 2.7 V) - JESD8B/JESD36 (2.7 V to 3.6 V). * 24 mA output drive (VCC = 3.0 V) * CMOS low power consumption * Latch-up performance exceeds 250 mA * Direct interface with TTL levels * Inputs accept voltages up to 5 V * Multiple package options * ESD protection: - HBM EIA/JESD22-A114-B exceeds 2000 V - MM EIA/JESD22-A115-A exceeds 200 V. * Specified from -40 C to +85 C and -40 C to +125 C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C. SYMBOL tPHL/tPLH PARAMETER propagation delay inputs nA, nB to output nY CONDITIONS VCC = 1.8 V; CL = 30 pF; RL = 1 k VCC = 2.5 V; CL = 30 pF; RL = 500 VCC = 2.7 V; CL = 50 pF; RL = 500 VCC = 3.3 V; CL = 50 pF; RL = 500 VCC = 5.0 V; CL = 50 pF; RL = 500 CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; (CL x VCC2 x fo) = sum of the outputs. 2. The condition is VI = GND to VCC. input capacitance power dissipation capacitance per gate VCC = 3.3 V; notes 1 and 2 DESCRIPTION
74LVC2G00
The 74LVC2G00 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. These feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74LVC2G00 provides the 2-input NAND gate.
TYPICAL 3.5 2.3 3.0 2.2 1.8 2.5 14 ns ns ns ns ns
UNIT
pF pF
2004 Sep 23
2
Philips Semiconductors
Product specification
Dual 2-input NAND gate
FUNCTION TABLE See note 1. INPUT nA L L H H Note 1. H = HIGH voltage level; L = LOW voltage level. ORDERING INFORMATION PACKAGE TYPE NUMBER 74LVC2G00DP 74LVC2G00DC 74LVC2G00DM PINNING PIN 1 2 3 4 5 6 7 8 1A 1B 2Y GND 2A 2B 1Y VCC SYMBOL data input 1A data input 1B data output 2Y ground (0 V) data input 2A data input 2B data output 1Y supply voltage DESCRIPTION TEMPERATURE RANGE -40 C to +125 C -40 C to +125 C -40 C to +125 C PINS 8 8 8 PACKAGE TSSOP8 VSSOP8 XSON8 MATERIAL plastic plastic plastic nB L H L H
74LVC2G00
OUTPUT nY H H H L
CODE SOT505-2 SOT765-1 SOT833-1
MARKING V00 V00 V00
2004 Sep 23
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Philips Semiconductors
Product specification
Dual 2-input NAND gate
74LVC2G00
00
1A 1 8 VCC
1A 1B 2Y GND
1 2 3 4
001aab736
8 7
VCC 1Y 2B 2A
1B
2
7
1Y
00
6 5
2Y
3
6
2B
GND
4
5
2A
001aab737
Transparent top view
Fig.1 Pin configuration TSSOP8 and VSSOP8.
Fig.2 Pin configuration XSON8.
handbook, halfpage handbook, halfpage
1 2
1 2 5 6
1A 1B 2A 2B
&
7
1Y
7
2Y
3
5 6
&
3
MNA712 MNA713
Fig.3 Logic symbol.
Fig.4 IEC logic symbol.
2004 Sep 23
4
Philips Semiconductors
Product specification
Dual 2-input NAND gate
74LVC2G00
handbook, halfpage
B Y A
MNA099
Fig.5 Logic diagram (one gate).
2004 Sep 23
5
Philips Semiconductors
Product specification
Dual 2-input NAND gate
RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO PARAMETER supply voltage input voltage output voltage active mode VCC = 1.65 V to 5.5 V; disable mode VCC = 0 V; Power-down mode Tamb tr, tf operating ambient temperature input rise and fall times VCC = 1.65 V to 2.7 V VCC = 2.7 V to 5.5 V CONDITIONS 0 0 0 0 -40 0 0 MIN. 1.65
74LVC2G00
MAX. 5.5 5.5 VCC 5.5 5.5 +125 20 10 V V V V V
UNIT
C ns/V ns/V
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO IO ICC, IGND Tstg PD Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. PARAMETER supply voltage input diode current input voltage output diode current output voltage output source or sink current VCC or GND current storage temperature power dissipation Tamb = -40 C to +125 C VI < 0 V note 1 VO > VCC or VO < 0 V active mode; notes 1 and 2 VO = 0 V to VCC CONDITIONS - -0.5 - -0.5 - - -65 - MIN. -0.5 MAX. +6.5 -50 +6.5 50 +6.5 50 100 +150 300 V mA V mA V mA mA C mW UNIT
VCC + 0.5 V
Power-down mode; notes 1 and 2 -0.5
2004 Sep 23
6
Philips Semiconductors
Product specification
Dual 2-input NAND gate
DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = -40 C to +85 C VIH HIGH-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VIL LOW-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VOL LOW-level output voltage VI = VIH or VIL IO = 100 A IO = 4 mA IO = 8 mA IO = 12 mA IO = 24 mA IO = 32 mA VOH HIGH-level output voltage VI = VIH or VIL IO = -100 A IO = -4 mA IO = -8 mA IO = -12 mA IO = -24 mA IO = -32 mA ILI Ioff ICC ICC input leakage current power OFF leakage current quiescent supply current additional quiescent supply current per pin VI = 5.5 V or GND VI or VO = 5.5 V VI = VCC or GND; IO = 0 A VI = VCC - 0.6 V; IO = 0 A 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 5.5 0 5.5 2.3 to 5.5 VCC - 0.1 1.2 1.9 2.2 2.3 3.8 - - - - - 1.53 2.13 2.50 2.60 4.10 0.1 0.1 0.1 5 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 - - - - - - - 0.08 0.14 0.19 0.37 0.43 0.65 x VCC - 1.7 2.0 0.7 x VCC - - - - - - - - - - - VCC (V) MIN. TYP.(1)
74LVC2G00
MAX.
UNIT
- - - - 0.7 0.8 0.3 x VCC 0.1 0.45 0.3 0.4 0.55 0.55 - - - - - - 5 10 10 500
V V V V V V V V V V V V V V V V V V V A A A A
0.35 x VCC V
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Philips Semiconductors
Product specification
Dual 2-input NAND gate
74LVC2G00
TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = -40 C to +125 C VIH HIGH-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VIL LOW-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VOL LOW-level output voltage VI = VIH or VIL IO = 100 A IO = 4 mA IO = 8 mA IO = 12 mA IO = 24 mA IO = 32 mA VOH HIGH-level output voltage VI = VIH or VIL IO = -100 A IO = -4 mA IO = -8 mA IO = -12 mA IO = -24 mA IO = -32 mA ILI Ioff ICC ICC Note 1. All typical values are measured at Tamb = 25 C. input leakage current power OFF leakage current quiescent supply current additional quiescent supply current per pin VI = 5.5 V or GND VI or VO = 5.5 V VI = VCC or GND; IO = 0 A VI = VCC - 0.6 V; IO = 0 A 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 5.5 0 5.5 2.3 to 5.5 VCC - 0.1 0.95 1.7 1.9 2.0 3.4 - - - - 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 - - - - - - VCC (V) MIN.
TYP.(1)
MAX.
UNIT
0.65 x VCC - 1.7 2.0 0.7 x VCC - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - 0.7 0.8 0.3 x VCC 0.1 0.70 0.45 0.60 0.80 0.80 - - - - - - 20 20 40 5000
V V V V V V V V V V V V V V V V V V V A A A A
0.35 x VCC V
2004 Sep 23
8
Philips Semiconductors
Product specification
Dual 2-input NAND gate
AC CHARACTERISTICS GND = 0 V. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = -40 C to +85 C tPHL/tPLH propagation delay nA, nB to nY see Figs 6 and 7 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 Tamb = -40 C to +125 C tPHL/tPLH propagation delay nA, nB to nY see Figs 6 and 7 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 Note 1. All typical values are measured at Tamb = 25 C. 1.2 0.7 0.7 0.7 0.5 - - - - - 1.2 0.7 0.7 0.7 0.5 3.5 2.3 3.0 2.2 1.8 VCC (V) MIN. TYP.(1)
74LVC2G00
MAX.
UNIT
8.6 4.8 5.6 4.3 3.3
ns ns ns ns ns
10.8 6.0 7.0 5.4 4.2
ns ns ns ns ns
2004 Sep 23
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Philips Semiconductors
Product specification
Dual 2-input NAND gate
AC WAVEFORMS
VI VM GND tPHL VOH nY output VOL VM tTHL tTLH
MNA218
74LVC2G00
handbook, halfpage
nA, nB input
tPLH
INPUT VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V VM 0.5 x VCC 0.5 x VCC 1.5 V 1.5 V 0.5 x VCC VCC VCC 2.7 V 2.7 V VCC VI tr = tf 2.0 ns 2.0 ns 2.5 ns 2.5 ns 2.5 ns
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.6 The input (nA, nB) to output (nY) propagation delays.
2004 Sep 23
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Philips Semiconductors
Product specification
Dual 2-input NAND gate
74LVC2G00
handbook, full pagewidth
VEXT VCC PULSE GENERATOR VI D.U.T. RT CL RL VO RL
MNA616
VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V
VI VCC VCC 2.7 V 2.7 V VCC
CL 30 pF 30 pF 50 pF 50 pF 50 pF
RL 1 k 500 500 500 500
VEXT tPLH/tPHL open open open open open tPZH/tPHZ GND GND GND GND GND tPZL/tPLZ 2 x VCC 2 x VCC 6V 6V 2 x VCC
Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.7 Load circuitry for switching times.
2004 Sep 23
11
Philips Semiconductors
Product specification
Dual 2-input NAND gate
PACKAGE OUTLINES
74LVC2G00
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c y HE vMA
Z
8
5
A pin 1 index
A2 A1
(A3)
Lp L
1
e bp
4
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 8 0
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16
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12
Philips Semiconductors
Product specification
Dual 2-input NAND gate
74LVC2G00
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A X
c y HE vMA
Z
8
5
Q A pin 1 index A2 A1 (A3) Lp L
1
e bp
4
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 8 0
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION
ISSUE DATE 02-06-07
2004 Sep 23
13
Philips Semiconductors
Product specification
Dual 2-input NAND gate
74LVC2G00
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 0.95 x 1.95 x 0.5 mm
SOT833-1
1
2
3
b 4 4x L
(2)
L1
e
8 e1
7 e1
6 e1
5
8x
(2)
A
A1 D
E
terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 2.0 1.9 E 1.0 0.9 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm
Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT833-1 REFERENCES IEC --JEDEC MO-252 JEITA --EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22
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Philips Semiconductors
Product specification
Dual 2-input NAND gate
DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
74LVC2G00
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2004 Sep 23
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Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R20/02/pp16
Date of release: 2004
Sep 23
Document order number:
9397 750 13771

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